For computing devices, “performance” is an umbrella term with many sides. One side is the quality of the “product” that results from the computations performed by the device, whether measured by objective criteria or by human observation. Another side is the energy the device expended to produce its product. In general, these two sides are in natural tension: Improving energy efficiency of a device may degrade the quality of its product; conversely, obtaining higher quality often worsens energy efficiency. However, the “you get what you pay for” principle only goes so far. Merely throwing more power at a quality-based problem might lead to device over-heating, which in turn might lead to even poorer quality.
When a computing device is portable and dependent on a limited supply of energy stored in a battery, improving performance in the sense of balancing power and quality becomes more important and more delicate, necessitating a smarter approach to energy usage. Improving some aspects of performance can be approached by reducing energy usage as much as possible while maintaining a minimum acceptable level of quality.
There are two parts to continually maintaining peak performance in this manner: monitoring performance and adjusting performance. These are cyclically related in that performance is adjusted in response to what monitoring reveals, and changes to the operational state of the computing device necessitates further monitoring. In particular, adjusting economizes energy according to the monitored levels of power and quality.
An obvious locus for economizing the energy consumption of a mobile computing device is a processor, such as a central processing unit (CPU) or a specialized co-processor, e.g., a graphics processing unit (GPU). A common practice in economizing the energy expended by a processor of a mobile computing device is the use of Dynamic Voltage/Frequency Scaling (DVFS), which is an algorithm for adjusting the voltage and/or frequency of a processor so as not to waste energy. The voltage and frequency are typically adjusted in tandem, because a higher voltage is generally needed to attain a higher frequency. Lowering the voltage lowers the power and therefore reduces the amount of energy consumed (and drawn from the battery). The basic principle is: Decrease the voltage (and power) of the processor if the accompanying decrease in its operating frequency will not adversely affect the quality of the device's product, as measured by some criterion.
One example of degraded quality—and a primary concern of this disclosure—is when the presentation of a sequence of images (also called “frames”) on a display unit of a mobile computing device does not progress as smoothly as intended. While smoothness is ultimately judged by a human observer, it can be quantified, for instance, by detecting when a frame is “dropped,” that is, is not rendered (i.e., prepared for presentation on the display unit) in time for an intended one of the display unit's Vsync (Vertical Synchronization) events, when the display unit can be refreshed. In turn, certain operational parameters of the device can be monitored and then used in a criterion for detecting a dropped frame.
A wide range of operational parameters of a device are also what are monitored by the device and used by a DVFS algorithm to decide how to adjust energy consumption. For example, the device's operating temperature can be an important consideration: If the device is too hot, it will use more power, making it even hotter, resulting in a race condition; thus, a DVFS module—software implementing the DVFS algorithm—may reduce processor voltage when a temperature sensor in the device reports to the DVFS module a temperature in excess of a pre-determined threshold.
Many of the operational parameters monitored and reported to the DVFS module pertain to the execution performance of the processor itself. Amongst such parameters (typically measured during a predetermined time interval or from the beginning of program execution) are: the total number of cycles performed, the total number of instructions executed, the number of stall cycles due to on/off-chip dependencies, the total number of data-cache misses, the total number of branch mispredictions, and so forth.
A standard behaviour of DVFS algorithms is to scale-down voltage and/or frequency of a processor in response to an indication that the processor is “idle” according to some criterion. In some systems, idleness may be determined by one or more of the following criteria: the number of cycles performed by the processor during a predetermined interval of time falls below a predetermined number, the number of instructions executed by the processor during a predetermined interval of time falls below a predetermined number, and the percentage of time the processor is executing instructions falls below a predetermined percentage. The theory behind designing a DVFS algorithm to scale-down frequency upon detecting processor idleness is that the processor is operating at a faster speed than necessary to do what it is tasked to do, thereby wasting energy.
It has been recognized that this standard strategy, while sound in many circumstances, is counterproductive in some other circumstances. This is because there are different reasons that a processor may be idle. It may happen that the processor is idle not because it has finished some task ahead of schedule, but because it has finished the task late, and the next task cannot begin right away; of particular interest to this disclosure is when the task of rendering a next frame cannot begin until the current frame has been presented on a display unit of a device, which can only take place at a specific time-point. The task might have finished late because the processor was not operating fast enough; in that case, its frequency should actually be scaled-up, not scaled-down. Alternatively, the task might have finished late because the processor, though operating at an appropriate speed, began the task at an inopportune time (i.e., it started “late,” perhaps due to a scheduling problem or another, higher-priority task); in that case, the frequency should not be changed at all. In either of these cases, the standard strategy of having the DVFS module scale-down frequency will backfire. In the former case, the processor will be even less capable of handling its tasks on the desired schedule; it may end up missing even more deadlines than had its speed not been changed. In the latter case, a frequency scale-down will likely cause deadlines to be missed that would have been met had the processor speed been left alone and had, in all likelihood, the tasks re-aligned with the desired schedule of deadlines. For ease of reference, DVFS algorithms that employ this standard strategy without exception are referred to herein as “classic” DVFS algorithms.
Existing solutions to the occasionally counterproductive behaviour of classic DVFS algorithms are more-sophisticated algorithms that are keyed to operational parameters other than or in addition to processor idleness. For instance, U.S. Pat. No. 7,698,575 to Samson (referred to hereinafter as “Samson”) teaches adjusting processor frequency based on a difference between a desired deadline (e.g., a Vsync event) and the actual completion time of a task (e.g., rendering a frame). If the difference is positive—i.e., the task is completed ahead of schedule—the DVFS module scales-down processor frequency; this concords with the behaviour of classic DVFS algorithms. If the difference is negative—i.e., the task is completed behind schedule—the frequency is scaled-up; this is the opposite of what a classic DVFS algorithm would do. This more-nuanced approach does, in some cases, avoid a classic DVFS algorithm's counterproductive behaviour.
Nevertheless, there are still other circumstances in which an algorithm in the style of Samson's will backfire. Although rendering frames in time for Vsync events is important, Samson's approach is fixated on monitoring and reacting to missed deadlines, oblivious to varying reasons for missed deadlines. It may happen that a deadline is missed even when the processor is operating at an appropriate speed, in which case a deadline-oriented DVFS algorithm will unnecessarily scale-up the frequency, only to then compensate for this mistake by reducing the speed back toward the original speed. In fact, as will be shown later, such an algorithm could also unnecessarily scale-down the frequency, only to then compensate for this mistake by increasing the speed back toward the original speed.
Thus, there is a need for more-reliable DVFS-based methods of monitoring and adjusting performance to economize energy consumption of a processor of a mobile computing device—while smoothly displaying a progression of images—methods which avoid the counterproductive adjustments sometimes perpetrated under existing DVFS approaches.
Like reference numerals have been used in different figures to denote like components.